By Edwin R Coover
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Extra info for ATM switches
One octet of ATM’s 5-octet header is dedicated to a header checksum. Error checking the AALs is summarized below: • AAL 1: AAL 1 adds a 1-octet header to each data block; this header contains sequencing, timing, and error-correcting information. Single bit errors can be corrected if required. • AAL 2: Neither the ITU-T nor ATM Forum have defined the specific format of AAL’s segmentation and reassembly (SAR) protocol data unit (PDU). The best prognostication is that AAL 2, if eventually specified, will be similar to AAL 1 and will include sequence checks and will detect/correct single bit errors.
In the WAN area, ATM switches are likely to eventually replace smart multiplexers, packet switches, routers, and frame relay equipment. Depending on the context, ATM can provide more efficient multiplexing, better QoS guarantees, or simply speed. The anticipation is that the data communications protocols transplanted (SNA, DECnet, TCP/IP, IPX) will be encapsulated using AAL 5. LANs can be viewed as a special case of legacy protocols. First, their ubiquity makes a smooth ATM transition an absolute necessity.
Reaching the desired party often became anticlimactic. In high-performance environments, a particular queuing problem called “head of the line” blockage is important to avoid. Technically, it is akin to “page faults” in virtual memory operating systems and the “fatal The Technical Challenges of High-Speed Switching I 41 embrace” in database systems; it involves a processing stoppage as a result of resource contention. For example, one is waiting in a bank queue and the teller cannot complete one’s transaction without the authorization of a bank officer, who is herself busy.